CS5535 datasheet(491/555 Pages) NSC

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PMC Register Descriptions (Continued)

5.18.3.8

PM Sleep Control Y De-assert Delay (PM_SCYD)

Reads always return the value written.

29:0

SLPX_END_

DELAY

Sleep X De-assert Delay. Indicates the number of 3.57954 MHz clock edges to wait

from Sleep wakeup before de-asserting the SLEEP_X ball. Bit 30 (SLPX_END_EN)

must be high to enable this delay.

If PCI_IDE_IN_SLP is not enabled (PMS I/O Offset 20h[30] = 0) or is less than the

SLPX_END_DELAY, SLEEP_X de-asserts at the same time the PCI/IDE inputs are re-

enabled.

PMS I/O Offset

1Ch

Type

R/W

Reset Value

00000000h

PM_SCYD Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876543210

SLPY_END_DELAY

PM_SCYD Bit Descriptions

Bit

Name

Description

RSVD

Reserved. By convention write 0, but may write anything.

SLPY_END_EN

Sleep Y De-assert and Delay Enable. Must be high to de-assert SLEEP_Y and

enable the delay specified in bits [29:0] (SLPY_END_DELAY).

29:0

SLPY_END_

DELAY

Sleep Control Y De-assert Delay. Indicates the number of 3.57954 MHz clock edges

to wait from Sleep wakeup before de-asserting the SLEEP_Y ball. Bit 30

(SLPY_END_EN) must be high to enable this delay.

If PCI_IDE_IN_SLP is not enabled (PMS I/O Offset 20h[30] = 0) or is less than the

SLPY_END_DELAY, SLEEP_Y de-asserts at the same time the PCI/IDE inputs are re-

enabled.

PM_SCXD Bit Descriptions

Bit

Name

Description

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