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CS5535 데이터시트(PDF) 122 Page - National Semiconductor (TI) |
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CS5535 데이터시트(HTML) 122 Page - National Semiconductor (TI) |
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122 / 555 page ![]() www.national.com 122 Revision 0.8 SMB Controller Functional Description (Continued) 4.10.1.8 Configuration SDA and SCL Signals The SDA and SCL are open-drain signals. The device per- mits the user to define whether to enable or disable the internal pull-up of each of these signals. SMB Clock Frequency The SMB permits the user to set the clock frequency for the System Management Bus clock. The clock is set by the SMBCTL2.SCLFRQ field and the SMBCTL3 register, which determines the SCL clock period used by the device. This clock low period may be extended by stall periods initi- ated by the SMB or by another System Management Bus device. In case of a conflict with another bus master, a shorter clock high period may be forced by the other bus master until the conflict is resolved. 4.10.1.9 Transaction Types Byte Write Sequence of events (see Figure 4-28): 1) START 2) Address phase 3) Acknowledge 4) Word address 5) Acknowledge 6) Data 7) Acknowledge 8) STOP Figure 4-28. SMB Byte Write Device Word Address Data Address SDA Line |
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