CS5535 datasheet(143/555 Pages) NSC

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LPC Port Functional Description (Continued)

Table 4-28. FWH Write Cycle

Signal

Clock

Cycle

LAD[3:0]

Peripheral

I/O

Description

START

1110b

On the rising edge of CLK with LFRAME# Low, the contents of

LAD[3:0] indicate the start of an FWH cycle.

IDSEL

0000

Indicates which FWH peripheral is selected. The value on the

LAD[3:0] is compared to the IDSEL strapping on the FWH device

pins to select which device is being addressed.

Note: From Intel(R) 82802 spec - the boot device must have an ID

(determined by ID strapping Pins ID[3:0]) of 0. It is advisable that

subsequent devices use incremental numbering.

ADDR

xxxx

A 28-bit address phase is transferred starting with the most signifi-

cant nibble first.

MSIZE

0000b

Always 0000b (single byte transfer).

DATA

xxxx

Data transfer is two cycles, starting with least significant nibble.

TAR

1111b

The LPC host drives LAD[3:0] to 1111b to indicate a turnaround

cycle.

TAR

1111b

(float)

The FWH device takes control of LAD[3:0] during this cycle.

SYNC

0000b

The FWH device drives LAD[3:0] to 0000b to indicate it has

received data or a command.

TAR

1111b

The FWH device drives LAD[3:0] to 1111b, indicating a turnaround

cycle.

TAR

1111b

(float)

N/A

The FWH device floats its output and the LPC host takes control of

LAD[3:0].

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