ST72340 datasheet(176/191 Pages) STMICROELECTRONICS

176 / 191 page

ST72340, ST72344, ST72345

176/191

ADC Characteristics

Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.

Notes:

1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-

lines and are not tested.

2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.

3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k

Ω). Data

based on characterization results, not tested in production.

4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then

always valid.

Figure 115. Typical A/D Converter Application

Notes:

1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-

pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.

2. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and

decreased to allow the use of a larger serial resistor (RAIN).

Symbol

Parameter

Conditions

Min

Typ 1)

Max

Unit

fADC

ADC clock frequency

0.4

MHz

VAIN

Conversion voltage range 2)

VSSA

VDDA

RAIN

External input resistor

10 3)

Ω

CADC

Internal sample and hold capacitor

tSTAB

Stabilization time after ADC enable

fCPU=8MHz, fADC=4MHz

0 4)

µs

tADC

Conversion time (Sample+Hold)

3.5

- Sample capacitor loading time

- Hold conversion time

1/fADC

IADC

Analog Part

Digital Part

0.2

AINx

ST72XXX

VDD

±1

µA

0.6V

CADC

6pF

VAIN

RAIN

10-Bit A/D

Conversion

Ω(max)

CAIN

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