CST12.0MTWA datasheet(138/153 Pages) STMICROELECTRONICS

138 / 153 page

ST72334J/N, ST72314J/N, ST72124J

138/153

16.12 8-BIT ADC CHARACTERISTICS

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Figure 98. Typical Application with ADC

Notes:

1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-

lines and are not tested.

2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS .

3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k

Ω). Data

based on characterization results, not tested in production.

4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then

always valid.

Symbol

Parameter

Conditions

Min

Typ 1)

Max

Unit

fADC

ADC clock frequency

MHz

VAIN

Conversion range voltage 2)

VSSA

VDDA

RAIN

External input resistor

10 3)

Ω

CADC

Internal sample and hold capacitor

tSTAB

Stabilization time after ADC enable

fCPU=8MHz, fADC=4MHz

0 4)

µs

tADC

Conversion time (Sample+Hold)

- Sample capacitor loading time

- Hold conversion time

1/fADC

AINx

ST72XXX

CIO

~2pF

VDD

±1

µA

0.6V

VAIN

RAIN

VDDA

VSSA

0.1

µF

VDD

ADC

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