ST72F324J2T3 datasheet(161/163 Pages) STMICROELECTRONICS

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ST72324

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16 IMPORTANT NOTES ON ST72F324B FLASH DEVICES:

With the objective of continuous improvement, ST

has developed new ST72F324B devices. These

devices are fully compatible with all ROM features

and provide an improved price/performance ratio

compared to the ST72F324 flash devices.

A summary of the technical improvements is given

below.

Refer to separate ST72324B datasheet for the or-

dering information and full specifications.

16.1 Reset Pin Logic levels

In ST72F324B Flash devices, the VIH/VIL levels for

the reset pin are the same as specified for ROM

devices

16.2 Wake-Up from Active Halt mode using

external interrupts

In ST72F324B Flash devices, any external inter-

rupt that capable of waking-up the MCU from Halt

mode can also wake-up the MCU from Active Halt

mode. Consequently note 1 below Table 8 on

page 36 does not apply to ‘B’ devices.

16.3 PLL Jitter

In ST72F324B Flash devices, PLL clock accuracy

is improved and the jitter is the same as specified

for ROM devices

16.4 Active Halt Power Consumption

In ST72F324B Flash devices, the power con-

sumption in Active Halt mode is specified as

230µA max. See Table 12.5.1 on page 120 for test

conditions.

16.5 Timer A Registers

In ST72F324B Flash devices, all Timer A registers

are present and their functionality is the same as

described for ROM devices in the ST72324B da-

tasheet.

ST72F324J2T3 데이터시트(PDF) 161 Page - STMicroelectronics