| 전자부품 데이터시트 검색엔진 |
|
ST72F262G2B6 데이터시트(PDF) 150 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST72F262G2B6 데이터시트(HTML) 150 Page - STMicroelectronics |
|
150 / 172 page ![]() ST72260Gx, ST72262Gx, ST72264Gx 150/172 13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin TA = -40 to +85°C unless otherwise specified Figure 90. Typical IPU on RESET pin Notes: 1. Data based on characterization results, not tested in production. 2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage Vss - 0.3 0.3xVDD V VIH Input high level voltage 0.7xVDD VDD + 0.3 Vhys Schmitt trigger voltage hysteresis1) 2.5 V VOL Output low level voltage 2) VDD=5V IIO=+5mA 0.68 0.95 V IIO=+2mA 0.28 0.45 RON Pull-up equivalent resistor VDD=5V 20 40 80 k Ω VDD=3V 85 tw(RSTL)out Generated reset pulse duration Internal reset sources 30 µs th(RSTL)in External reset pulse hold time 3) 20 µs tg(RSTL)in Filtered glitch duration 200 ns 0 50 100 150 200 250 2.43 4 5 5.56 Vdd (V) T=25C T=90C T=-45C |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |