ST92F124 datasheet(228/429 Pages) STMICROELECTRONICS

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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)

INTERRUPT VECTOR REGISTER (S_IVR)

R244 - Read/Write

Reset value: undefined

Bit 7:3 = V[7:3]: SCI Interrupt Vector Base Ad-

dress.

User programmable interrupt vector bits for trans-

mitter and receiver.

Bit 2:1 = EV[2:1]: Encoded Interrupt Source.

Both bits EV2 and EV1 are read only and set by

hardware according to the interrupt source.

Bit 0 = D0: This bit is forced by hardware to 0.

ADDRESS/DATA COMPARE REGISTER (ACR)

R245 - Read/Write

Reset value: undefined

Bit 7:0 = AC[7:0]: Address/Compare Character.

With either 9th bit address mode, address after

break mode, or character search, the received ad-

dress will be compared to the value stored in this

ter content, the Receiver Address Pending bit

(RXAP in the S_ISR register) is set. After the

RXAP bit is set in an addressed mode, all received

data words will be transferred to the Receiver Buff-

er Register.

EV2

EV1

EV2 EV1

Interrupt source

Receiver Error (Overrun, Framing, Parity)

Break Detect or Address Match

Received Data Pending/Receiver DMA

End of Block

Transmitter buffer or shift register empty

transmitter DMA End of Block

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

ST92F124 데이터시트(PDF) 228 Page - STMicroelectronics

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