ST92F124 datasheet(319/429 Pages) STMICROELECTRONICS

319 / 429 page

319/429

J1850 Byte Level Protocol Decoder (JBLPD)

J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)

Bit 5 = DMASUSP DMA Suspended Selector.

If this bit is “0”, JBLPD DMA has higher priority

with respect to the Interrupts of the peripheral.

DMA is performed even if an interrupt request is

already scheduled or if the relative interrupt rou-

tine is in execution.

If the bit is “1”, while the ERROR or TLA flag of the

STATUS register are set, the DMA transfers are

suspended. As soon as the flags are reset, the

DMA transfers can be performed.

0: DMA not suspended

1: DMA suspended

Note: This bit has effect only on the priorities of

the JBLPD peripheral.

Bit 4 = LOOPB Local Loopback Selector.

This bit allows the Local Loopback mode. When

this mode is enabled (LOOPB=1), the VPWO out-

put of the peripheral is sent to the VPWI input with-

out inversions whereas the VPWO output line of

the MCU is placed in the passive state. Moreover

the VPWI input of the MCU is ignored by the pe-

ripheral. (Refer to Figure 138).

0: Local Loopback disabled

1: Local Loopback enabled

Note: When the LOOPB bit is set, also the INPOL

bit must be set to obtain the correct management

of the polarity.

Bit 3:0 = RSEL[3:0] Registers Group Selection

bits.

These four bits are used to select one of the 9

groups of registers, each one composed of four

registers that are stacked at the addresses from

R252 (FCh) to R255 (FFh) of this register page

(23). Unless the wanted registers group is already

selected, to address a specific registers group,

these bits must be correctly written.

This feature allows that 36 registers (4 DMA regis-

ters - RDADR, RDCPR, TDAPR, TDCPR - and 32

Message Filtering Registers - FREG[0:31]) are

mapped using only 4 registers (here called Current

Registers - CREG[3:0]).

Since

the

Message

Filtering

Registers

(FREG[0:31]) are seldom read or written, it is sug-

gested to always reset the RSEL[3:0] bits after ac-

cessing the FREG[0:31] registers. In this way the

DMA registers are the current registers.

ST92F124 데이터시트(PDF) 319 Page - STMicroelectronics

ST92F124 데이터시트(HTML) 319 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL