PQFP100 datasheet(206/429 Pages) STMICROELECTRONICS

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MULTIFUNCTION TIMER (MFT)

MULTIFUNCTION TIMER (Cont’d)

OUTPUT A CONTROL REGISTER (OACR)

R252 - Read/Write

Reset value: 0000 0000

Bits 7:6 = C0E[0:1]: COMP0 action bits.

These bits are set and cleared by software. They

configure the action to be performed on the Tx-

OUTA pin when a successful compare of the

CMP0R register occurs. Refer to Table 42 for the

list of actions that can be configured.

Bits 5:4 = C1E[0:1]: COMP1 action bits.

These bits are set and cleared by software. They

configure the action to be performed on the Tx-

OUTA pin when a successful compare of the

CMP1R register occurs. Refer to Table 42 for the

list of actions that can be configured.

Bits 3:2 = OUE[0:1]: OVF/UNF action bits.

These bits are set and cleared by software. They

configure the action to be performed on the Tx-

OUTA pin when an Overflow or Underflow of the

U/D counter occurs. Refer to Table 42 for the list of

actions that can be configured.

Table 42. Output A Action Bits

Notes:

– xx stands for C0, C1 or OU.

– Whenever more than one event occurs simulta-

neously, Action bit 0 will be the result of ANDing

Action bit 0 of all simultaneous events and Action

bit 1 will be the result of ANDing Action bit 1 of all

simultaneous events.

Bit 1 = CEV: On-Chip event on CMP0R.

This bit is set and cleared by software.

0: No action

1: A successful compare on CMP0R activates the

on-chip event signal (a single pulse is generat-

ed)

Bit 0 = OP: TxOUTA preset value.

This bit is set and cleared by software and by hard-

ware. The value of this bit is the preset value of the

TxOUTA pin. Reading this bit returns the current

state of the TxOUTA pin (useful when it is selected

in toggle mode).

C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 CEV 0P

xxE0

xxE1

Action on TxOUTA pin when an xx

event occurs

Set

Toggle

Reset

NOP

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