PCF5083HSLASHF2 datasheet(110/136 Pages) PHILIPS

110 / 136 page

1996 Oct 29

110

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

Table 94 Parallel Port Data Register

Note

1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘

−’ denotes not affected from reset line.

During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other

registers are undefined and have to be set by the controller.

Table 95 Parallel Port Data Direction Register

Note

1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘

−’ denotes not affected from reset line.

During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other

registers are undefined and have to be set by the controller.

Table 96 System Conﬁguration Register (SYSCON)

Note

1. RSTx = 0 means reset condition if either RSTO or RSTC is asserted; ‘

−’ denotes not affected from reset line.

During reset (RST, RSTO, RSTC) only those registers with an explicitly given reset value are affected. All other

registers are undefined and have to be set by the controller.

BIT

R/W

SYMBOL

OPERATION

RST=0

RSTx=0(1)

0 to 5

R/W

PIO0_DATA to PIO5_DATA

PIO0 to PIO5 input or output data

−

BIT

R/W

SYMBOL

OPERATION

RST=0

RSTx=0(1)

PIO0_DDIR

reserved

−

1 to 5

R/W

PIO1_DDIR to PIO5_DDIR

A logic 1 selects the port as an output.

A logic 0 selects the port as an input.

−

BIT

R/W

SYMBOL

OPERATION (if bit is set)

RST = 0

RSTx=0(1)

CLK13M

Disable the CLK13M output pin.

−

CLK20M

Disable the CLK20M output pin.

−

CLK32K

Disable the CLK32K output pin; PCF5083-2B and

PCF5083-2C only.

−

CLK26M

Disable the CLK26M output pin; PCF5083-3A only.

−

DSP_CLK0

These two bits select the DSP core input clock.

−

DSP_CLK1

−

RS232_CLK

Select the external clock for the RS232 interface

−

LOCK

When a logic 1, the PLL is out of lock. When a logic 0,

the PLL is in lock.

−

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