PCF5083HSLASHF2 datasheet(115/136 Pages) PHILIPS

115 / 136 page

1996 Oct 29

115

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

13 TEST AND EMULATION MODES

The PCF5083 supports two test and emulation modes which make all internal signals of the DSP or Timer core externally

available. These test modes are selected with either DSPEN = 1 and TIMEN = 0, or DSPEN = 0 and TIMEN = 1.

More information on these test modes will be made available with application notes. Ask your local sales office about the

status of these application notes.

14 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. Stresses above those listed under Maximum Absolute Ratings may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at these or any other condition above those indicated in

the operation section of this specification is not implied.

2. For operating at elevated temperatures the device must be derated based on 125

°C maximum junction temperature.

3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects

of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any

voltage larger than the rated maxima.

15 DC CHARACTERISTICS

Tamb = −40 to +85 °C; VDD = 3.3 V ±10%.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

VDD

supply voltage

−0.5

+5.0

input voltage on any pin with respect to ground (VSS))

−0.5

VDD + 0.5V

sink current into any pin

−20

+20

Ptot

total power dissipation

−

800

Tstg

storage temperature

−65

+150

°C

Tamb

operating ambient temperature

−40

+85

°C

SYMBOL

PARAMETER(1)

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

VDD

operating supply voltage

2.7

3.0

3.6

IDD

operating supply current

all sections operating;

Timer active, DSP encoding

speech; note 2

I(VDD2) +I(VDDPLL)

−

I(VDD1)

note 3

−

IDDtot

I(VDD2) +I(VDDPLL) +I(VDD1)

−

IDD(SLP)

supply current Sleep mode

Timer sleeping, DSP

inactive

I(VDD2) +I(VDDPLL)

−

250

500

µA

I(VDD1)

note 3

−

340

−µA

IDD(SLP)tot

I(VDD2) +I(VDDPLL) +I(VDD1)

−

590

−µA

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