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전자부품 데이터시트 검색엔진 |
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I.MX8 데이터시트(PDF) 1 Page - NXP Semiconductors |
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I.MX8 데이터시트(HTML) 1 Page - NXP Semiconductors |
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1 / 148 page  Ordering Information See Table 2 on page 5 MIMX8QPnAVUFEAx NXP Semiconductors Data Sheet: Technical Data IMX8QP1P3AEC Rev. 0, 03/2024 Package Information 29 x 29 mm package case outline © 2024 NXP B.V. NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 1 Introduction The i.MX 8 Family consists of two processors: i.MX 8QuadMax and 8QuadPlus. This data sheet covers the i.MX 8QuadPlus processor, which is composed of seven cores (one Arm® Cortex®-A72, four Arm Cortex®-A53, and two Arm Cortex®-M4F), dual 32-bit GPU subsystems, 4K H.265 capable VPU, and dual failover-ready display controllers. This processor supports a single 4K display (with multiple display output options, including MIPI-DSI, HDMI, eDP/DP, and LVDS), or multiple smaller displays. Memory interfaces supporting LPDDR4, Quad SPI/Octal SPI (FlexSPI), eMMC 5.1, RAW NAND, SD 3.0, and a wide range of peripheral I/Os such as PCIe, provide wide flexibility. Advanced multicore audio processing is supported by the Arm cores and a high performance Tensilica® HiFi 4 DSP for pre- and post-audio processing as well as voice recognition. i.MX 8QuadPlus 1.3GHz Automotive and Infotainment Applications Processors 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 System Controller Firmware (SCFW) Requirements5 1.3 Related resources . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 13 3.2 Recommended Connections for Unused Interfaces13 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 Power supplies requirements and restrictions. . . . 26 4.3 PLL electrical characteristics. . . . . . . . . . . . . . . . . 29 4.4 On-chip oscillators. . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36 4.6 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 42 4.7 Output Buffer Impedance Parameters. . . . . . . . . . 45 4.8 System Modules Timing . . . . . . . . . . . . . . . . . . . . 49 4.9 General-Purpose Media Interface (GPMI) Timing. 53 4.10 External Peripheral Interface Parameters . . . . . . . 62 4.11 Analog-to-digital converter (ADC) . . . . . . . . . . . . 111 5 Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 115 5.1 Boot mode configuration inputs. . . . . . . . . . . . . . 115 5.2 Boot devices interfaces allocation. . . . . . . . . . . . 115 6 Package information and contact assignments . . . . . . 117 6.1 FCPBGA, 29 x 29 mm, 0.75 mm pitch . . . . . . . . 117 |
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