MFS5600AMBAFES datasheet(116/118 Pages) NXP

116 / 118 page

NXP Semiconductors

FS5600

Automotive buck regulator and controller with voltage monitors and watchdog timer

Figures

Fig. 1.

FS5600 Functional block diagram .....................2

Fig. 2.

FS5600 internal block diagram ......................... 6

Fig. 3.

Regulator input options ..................................... 7

Fig. 4.

QM version pinout .............................................8

Fig. 5.

ASIL B, and enhanced ASIL B version

pinout .................................................................8

Fig. 6.

SW1 high-level block diagram .........................14

Fig. 7.

SW1 output voltage setting using an

external resistor divider ...................................16

Fig. 8.

SW2 high-level block diagram .........................22

Fig. 9.

SW2 application schematic with Rshunt

current sensing ................................................25

Fig. 10.

DCR current sense with a single capacitor ......25

Fig. 11.

Clock management system high-level block

diagram ............................................................33

Fig. 12.

Windowed watchdog concept ..........................45

Fig. 13.

Challenger watchdog formula ..........................47

Fig. 14.

Watchdog error counter configurations ............49

Fig. 15.

Watchdog refresh counter configurations ........ 50

Fig. 16.

FCCU 1/2 bi-stable protocol example ............. 50

Fig. 17.

Low-level ERRMONx detected as error .......... 52

Fig. 18.

8-bit CRC Polynomial ......................................55

Fig. 19.

FS5600 state diagram .....................................60

Fig. 20.

SW1 Soft-start .................................................92

Fig. 21.

SW1 Load Transient Response ...................... 92

Fig. 22.

SW2 Load Transient Response ...................... 93

Fig. 23.

SW1 Dropout Performance ............................. 93

Fig. 24.

SW2 Dropout Performance ............................. 94

Fig. 25.

SW1 Efficiency (12 Vin, 450 kHz) ................... 94

Fig. 26.

SW2 Efficiency (12 Vin, 450 kHz) ................... 94

Fig. 27.

SW1 Efficiency (5 Vout, 450 kHz) ................... 95

Fig. 28.

SW2 Efficiency (5 Vout, 450 kHz) ................... 95

Fig. 29.

SW1 Load Regulation ..................................... 95

Fig. 30.

SW2 Load Regulation ..................................... 96

Fig. 31.

Typical application block diagram ....................97

Fig. 32.

Example power up and power down

waveforms ....................................................... 98

Fig. 33.

Typical application schematic ..........................99

Fig. 34.

Package outline HVQFN32

(SOT617-24(SC)) – ES version (wettable

flank) ..............................................................100

Fig. 35.

Package outline detail HVQFN32

(SOT617-24(SC)) – ES version (wettable

flank) ..............................................................101

Fig. 36.

PCB design guidelines – solder

mask opening pattern for HVQFN32

(SOT617-24(SC)) – ES version (wettable

flank) ..............................................................102

Fig. 37.

PCB guidelines – I/O pads and solderable

area for HVQFN32 (SOT617-24(SC)) – ES

version (wettable flank) ................................. 103

Fig. 38.

PCB design guidelines – solder paste

stencil for HVQFN32 (SOT617-24(SC)) –

ES version (wettable flank) ........................... 104

Fig. 39.

Package outline note HVQFN32

(SOT617-24(SC)) – ES version (wettable

flank) ..............................................................105

Fig. 40.

Package outline HVQFN32

(SOT617-24(SC)) – EP version (non-

wettable flank) ............................................... 106

Fig. 41.

Package outline detail HVQFN32

(SOT617-24(SC)) – EP version (non-

wettable flank) ............................................... 107

Fig. 42.

PCB design guidelines – solder

mask opening pattern for HVQFN32

(SOT617-24(SC)) – EP version (non-

wettable flank) ............................................... 108

Fig. 43.

PCB guidelines – I/O pads and solderable

area for HVQFN32 (SOT617-24(SC)) – EP

version (non-wettable flank) .......................... 109

Fig. 44.

PCB design guidelines – solder paste

stencil for HVQFN32 (SOT617-24(SC)) –

EP version (non-wettable flank) .................... 110

Fig. 45.

Package outline note HVQFN32

(SOT617-24(SC)) – EP version (non-

wettable flank) ............................................... 111

FS5600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 29 April 2024

116 / 118

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