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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DSPIC30F6015T-30E/PT 데이터시트(PDF) 60 Page - Microchip Technology |
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DSPIC30F6015T-30E/PT 데이터시트(HTML) 60 Page - Microchip Technology |
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60 / 236 page  dsPIC30F6010A/6015 DS70150C-page 58 © 2007 Microchip Technology Inc. FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE 8.2 Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their correspond- ing TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will not convert an ana- log input. Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. 8.2.1 I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically this instruction would be a NOP. EXAMPLE 8-1: PORT WRITE/READ EXAMPLE Q D CK WR LAT + TRIS Latch I/O Pad WR Port Data Bus Q D CK Data Latch Read LAT Read Port Read TRIS 1 0 1 0 WR TRIS Peripheral Output Data Peripheral Input Data I/O Cell Peripheral Module Peripheral Output Enable PIO Module Output Multiplexers Input Data Peripheral Module Enable Output Enable Output Data MOV 0xFF00, W0 ; Configure PORTB<15:8> ; as inputs MOV W0, TRISBB ; and PORTB<7:0> as outputs NOP ; Delay 1 cycle BTSS PORTB, #13 ; Next Instruction |
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