PIC16F883-ESLASHSOSQTP datasheet(200/288 Pages) MICROCHIP

200 / 288 page

PIC16F882/883/884/886/887

DS41291D-page 198

Preliminary

FIGURE 13-18:

STOP CONDITION RECEIVE OR TRANSMIT MODE

13.4.12

CLOCK ARBITRATION

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

de-asserts the SCL pin (SCL allowed to float high).

When the SCL pin is allowed to float high, the Baud

Rate Generator (BRG) is suspended from counting

until the SCL pin is actually sampled high. When the

SCL pin is sampled high, the Baud Rate Generator is

reloaded with the contents of SSPADD<6:0> and

begins counting. This ensures that the SCL high time

will always be at least one BRG rollover count, in the

event that the clock is held low by an external device

(Figure 13-19).

13.4.13

SLEEP OPERATION

While in Sleep mode, the I2C module can receive

addresses or data, and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if the MSSP interrupt is enabled).

13.4.14

EFFECT OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

FIGURE 13-19:

CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE

SCL

SDA

SDA asserted low before rising edge of clock

Write to SSPCON2

Set PEN

Falling edge of

SCL = 1 for TBRG, followed by SDA = 1 for TBRG

9th clock

SCL brought high after TBRG

Note: TBRG = one Baud Rate Generator period.

TBRG

after SDA sampled high, P bit (SSPSTAT) is set

TBRG

to set up Stop condition

ACK

TBRG

PEN bit (SSPCON2) is cleared by

hardware and the SSPIF bit is set

SCL

SDA

BRG overflow,

Release SCL,

If SCL = 1, load BRG with

SSPADD<6:0>, and start count

BRG overflow occurs,

Release SCL, Slave device holds SCL low

SCL = 1, BRG starts counting

clock high interval

SCL line sampled once every machine cycle (TOSC*4),

Hold off BRG until SCL is sampled high

TBRG

to measure high time interval

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