RELEASED

PM7350 S/UNI-DUPLEX

DATA SHEET

PMC-1980581

ISSUE 5

DUAL SERIAL LINK PHY MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

i

CONTENTS

1

FEATURES .............................................................................................. 1

2

APPLICATIONS ....................................................................................... 3

3

REFERENCES......................................................................................... 4

4

APPLICATION EXAMPLES ..................................................................... 5

5

BLOCK DIAGRAM ..................................................................................11

6

DESCRIPTION ...................................................................................... 12

7

PIN DIAGRAM ....................................................................................... 14

8

PIN DESCRIPTION................................................................................ 15

9

FUNCTIONAL DESCRIPTION............................................................... 45

9.1

PARALLEL BUS INTERFACE ..................................................... 45

9.2

CLOCKED SERIAL DATA INTERFACE ...................................... 57

9.3

HIGH-SPEED SERIAL INTERFACE ........................................... 61

9.4

CELL BUFFERING AND FLOW CONTROL ............................... 71

9.5

TIMING REFERENCE INSERTION AND RECOVERY ............... 75

9.6

JTAG TEST ACCESS PORT....................................................... 76

9.7

MICROPROCESSOR INTERFACE ............................................ 76

9.8

INTERNAL REGISTERS ............................................................. 80

9.9

REGISTER MEMORY MAP ........................................................ 80

10

NORMAL MODE REGISTER DESCRIPTION ....................................... 84

11

TEST FEATURES DESCRIPTION ...................................................... 170

11.1 RAM BUILT-IN-SELF-TEST ...................................................... 173

11.2 JTAG TEST PORT .................................................................... 177