ST10F269ZX datasheet(141/184 Pages) STMICROELECTRONICS

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ST10F269

21 - ELECTRICAL CHARACTERISTICS

141/184

Notes: 1. ST10F269 pins are equipped with low-noise output drivers which significantly improve the device’s EMI performance. These

low-noise drivers deliver their maximum current only until the respective target output level is reached. After this, the output current

is reduced. This results in increased impedance of the driver, which attenuates electrical noise from the connected PCB tracks. The

current specified in column “Test Conditions” is delivered in any cases.

2. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the

voltage results from the external circuitry.

3. Partially tested, guaranteed by design characterization.

4. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified

range (i.e. VOV > VDD+0.5V or VOV < -0.5V). The absolute sum of input overload currents on all port pins may not exceed 50mA. The

supply voltage must remain within the specified limits.

5. This specification is only valid during Reset, or during Hold-mode or Adapt-mode. Port 6 pins are only affected if they are used for

CS output and if their open drain function is not enabled.

6. The maximum current may be drawn while the respective signal line remains inactive.

7. The minimum current must be drawn in order to drive the respective signal line active.

8. The power supply current is a function of the operating frequency. This dependency is illustrated in Figure 65 and Figure 65. These

parameters are tested at VDDmax and 40MHz (or 32MHz) CPU clock with all outputs disconnected and all inputs at VIL or VIH. The

chip is configured with a demultiplexed 16-bit bus, direct clock drive, 5 chip select lines and 2 segment address lines, EA pin is low

during reset. After reset, PORT 0 is driven with the value ‘00CCh’ that produces infinite execution of NOP instruction with 15

wait-states, R/W delay, memory tristate wait state, normal ALE. Peripherals are not activated.

9. Idle mode supply current is a function of the operating frequency. This dependency is illustrated in the Figure 65. These

parameters are tested at VDDmax and 40MHz (or 32MHz) CPU clock with all outputs disconnected and all inputs at VIL or VIH.

10. This parameter value includes leakage currents. With all inputs (including pins configured as inputs) at 0V to 0.1V or at

VDD – 0.1V to VDD, VREF = 0V, all outputs (including pins configured as outputs) disconnected.

11. Typical IPD value is 5µA @ TA=25°C, 20µA @ TA=85°C and 60µA @ TA=125°C.

12. Partially tested, guaranteed by design characterization using 22pF loading capacitors on crystal pins.

IPD2

Power-down mode supply current (Real time

clock enabled, oscillator enabled)

VDD = 5.5V

TA = 55°C

fOSC = 25MHz

–

2 + fOSC / 4

Symbol

Parameter

Test

Conditions

Min.

Max.

Unit

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