ST10F269ZX datasheet(171/184 Pages) STMICROELECTRONICS

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ST10F269

171/184

21.4.13 - External Bus Arbitration

VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF (PQFP144 devices)

Note: 1. Partially tested, guaranteed by design characterization

VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF (TQFP144 devices)

Note: 1. Partially tested, guaranteed by design characterization

Symbol

Parameter

Maximum CPU Clock

= 40 MHz

Variable CPU Clock

1/2TCL = 1 to 40 MHz

Minimum

Maximum

Minimum

Maximum

t61

HOLD input setup time

to CLKOUT

–

t62

CLKOUT to HLDA high

or BREQ low delay

–

12.5

–

12.5

t63

CLKOUT to HLDA low

or BREQ high delay

–

12.5

–

12.5

t64

CSx release

–

t65

CSx drive

-4

t66

Other signals release

–

t67

Other signals drive

-4

Symbol

Parameter

Maximum CPU Clock

= 32MHz

Variable CPU Clock

1/2TCL = 1 to 32MHz

Unit

Minimum

Maximum

Minimum

Maximum

t61

HOLD input setup time

to CLKOUT

–

t62

CLKOUT to HLDA high

or BREQ low delay

–

15.625

–

15.625

t63

CLKOUT to HLDA low

or BREQ high delay

–

15.625

–

15.625

t64

CSx release

–15

–

t65

CSx drive

-4

t66

Other signals release

–15

–

t67

Other signals drive

-4

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