STM32G473MB datasheet(153/229 Pages) STMICROELECTRONICS

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DS12712 Rev 5

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STM32G473xB STM32G473xC STM32G473xE

Electrical characteristics

194

tSETTLING

Settling time (full scale: for

a 12-bit code transition

between the lowest and the

highest input codes when

DAC_OUT reaches final

value)

VDDA<2,7V

With One comparator

on DAC output

10%-90%

5%-95%

116

1%-99%

181

32lsb

196

1lsb

332

VDDA<2,7V

With One comparator

and OPAMP on DAC

output

10%-90%

128

5%-95%

170

1%-99%

265

32lsb

284

1lsb

483

tWAKEUP(2)

Wakeup time from off state

(setting the ENx bit in the

DAC Control register) until

final value ±1 LSB

Normal mode CL ≤ 10 pF

1.4

3.5

µs

PSRR

VDDA supply rejection ratio

VDD > 2.7 V

VDD <2.7 V

tSAMP

Sampling time in sample

and hold mode (code

transition between the

lowest input code and the

highest input code when

DACOUT reaches final

value ±1LSB)

0.7

µs

CIint

Internal sample and hold

capacitor

dV/dt (hold

phase)

Voltage decay rate in

Sample and hold mode,

during hold phase

CSH = 4 pF

T = 55°C

-50

mV/ms

IDDA(DAC)

DAC consumption from

VDDA

No load, middle code (0x800)

0.2

µA

IDDV(DAC)

DAC consumption from

VREF+

No load, middle code (0x800)(3)

-720

955

1. Guaranteed by design - Not tested in production.

2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

3. Worst case consumption is at code 0x800.

Table 71. DAC 15MSPS characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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