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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST7FLITE25F2M6 데이터시트(PDF) 114 Page - STMicroelectronics |
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ST7FLITE25F2M6 데이터시트(HTML) 114 Page - STMicroelectronics |
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114 / 133 page  ST7LITE2 114/133 COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 87. SPI Slave Timing Diagram with CPHA=1 1) Figure 88. SPI Master Timing Diagram 1) Notes: 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD. 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration. SS INPUT CPHA=0 MOSI INPUT MISO OUTPUT CPHA=0 tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) tsu(SI) th(SI) MSB OUT BIT6 OUT LSB OUT see CPOL=0 CPOL=1 tsu(SS) th(SS) tdis(SO) th(SO) see note 2 note 2 tc(SCK) HZ tv(SO) MSB IN LSB IN BIT1 IN SS INPUT CPHA=0 MOSI OUTPUT MISO INPUT CPHA=0 CPHA=1 CPHA=1 tc(SCK) tw(SCKH) tw(SCKL) th(MI) tsu(MI) tv(MO) th(MO) MSB IN MSB OUT BIT6 IN BIT6 OUT LSB OUT LSB IN seenote2 seenote2 CPOL=0 CPOL=1 CPOL=0 CPOL=1 tr(SCK) tf(SCK) |
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