ST10F273 datasheet(151/179 Pages) STMICROELECTRONICS

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ST10F273

Electrical characteristics

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Figure 44.

ST10F273 PLL jitter

24.8.10

PLL lock / unlock

During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the

CPU is generated, and the reference clock (oscillator) is automatically disconnected from

the PLL input: in this way, the PLL goes into free-running mode, providing the system with a

backup clock signal (free running frequency Ffree). This feature allows to recover from a

crystal failure occurrence without risking to go in an undefined configuration: the system is

provided with a clock allowing the execution of the PLL unlock interrupt routine in a safe

mode.

The path between reference clock and PLL input can be restored only by a hardware reset,

or by a bidirectional software or watchdog reset event that forces the RSTIN pin low.

Note:

The external RC circuit on RSTIN pin shall be properly sized in order to extend the duration

of the low pulse to grant the PLL gets locked before the level at RSTIN pin is recognized

high: bidirectional reset internally drives RSTIN pin low for just 1024 TCL (definitively not

sufficient to get the PLL locked starting from free-running mode).

N (CPU clock periods)

200

400

±5

±1

800

600

1000

1200

1400

64MHz

±2

±3

±4

24MHz

40MHz

32MHz

16MHz

TJIT

Table 71.

PLL characteristics [VDD = 5V ± 10%, VSS = 0V, TA = –40°C to +125°C]

Symbol

Parameter

Conditions

Value

Unit

Min.

Max.

TPSUP

PLL start-up time (1)

Stable VDD and reference clock

–

300

µs

TLOCK

PLL lock-in time

Stable VDD and reference clock,

starting from free-running mode

–

250

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