ST72F521 datasheet(185/215 Pages) STMICROELECTRONICS

185 / 215 page

ST72F521, ST72521B

185/215

12.9 CONTROL PIN CHARACTERISTICS

12.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels.

3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

the RESET pin with a duration below th(RSTL)in can be ignored.

5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-

vironments.

6. Data guaranteed by design, not tested in production.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage 1)

0.16xVDD

VIH

Input high level voltage 1)

0.85xVDD

Vhys

Schmitt trigger voltage hysteresis 2)

2.5

VOL

Output low level voltage 3)

VDD=5V

IIO=+2mA

0.2

0.5

IIO

Input current on RESET pin

RON

Weak pull-up equivalent resistor

120

Ω

tw(RSTL)out Generated reset pulse duration

Stretch applied on

external pulse

0426)

µs

Internal reset sources

426)

µs

th(RSTL)in External reset pulse hold time

2.5

µs

tg(RSTL)in Filtered glitch duration

200

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