ST72F521 datasheet(193/215 Pages) STMICROELECTRONICS

193 / 215 page

ST72F521, ST72521B

193/215

12.12 10-BIT ADC CHARACTERISTICS

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Notes:

1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k

Ω). Data

based on characterization results, not tested in production.

2. For Flash devices: injecting negative current on any of the analog input pins significantly reduces the accuracy of any

conversion being performed on any analog input. Analog pins of flash devices can be protected against negative injection

by adding a Schottky diode (pin to ground). Injecting negative current on digital input pins degrades ADC accuracy espe-

cially if performed on a pin close to the analog input pins. Any positive injection current within the limits specified for

IINJ(PIN) and ΣIINJ(PIN) in Section 12.8 does not affect the ADC accuracy.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fADC

ADC clock frequency

0.4

MHz

VAREF

Analog reference voltage

0.7*VDD ≤VAREF ≤VDD

3.8

VDD

VAIN

Conversion voltage range 1)

VSSA

VAREF

Ilkg

Positive input leakage current for analog

input

-40°C

≤TA≤85°C range

±250

Other TA ranges

±1

µA

Negative input leakage current on ro-

bust analog pins (ROM devices only)2

VIN<VSS, | IIN |< 400µA

on adjacent robust ana-

log pin

µA

Ilkg

Positive input leakage current for analog

input

-40°C

≤TA≤85°C range

±250

Other TA ranges

±1

µA

Negative input leakage current on ro-

bust analog pins (ROM devices only)2

VIN<VSS, | IIN |< 400µA

on adjacent robust ana-

log pin

µA

RAIN

External input impedance

see

Figure

110 and

Figure

1112)3)4)

Ω

CAIN

External capacitor on analog input

fAIN

Variation freq. of analog input signal

CADC

Internal sample and hold capacitor

tADC

Conversion time (Sample+Hold)

fCPU=8MHz, SPEED=0 fADC=2MHz

7.5

µs

tADC

- No of sample capacitor loading cycles

- No. of Hold conversion cycles

1/fADC

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