ST10F271 datasheet(166/173 Pages) STMICROELECTRONICS

166 / 173 page

Electrical characteristics

ST10F271

166/173

Figure 60.

External bus arbitration (regaining the bus)

This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated

earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be

deactivated without the ST10F271 requesting the bus.

The next ST10F271 driven bus cycle may start here.

24.8.20

High-speed synchronous serial interface (SSC) timing

Master mode

VDD = 5V ±10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF

CLKOUT

HOLD

HLDA

Other

signals

t62

CSx

(On P6.x)

t67

t62

t65

t61

BREQ

t63

t62

Table 81.

SSC master mode timings

Symbol

Parameter

Max. Baudrate 6.6MBd

(1)@F

CPU = 40MHz

(<SSCBR> = 0002h)

Variable Baudrate

(<SSCBR> = 0001h -

FFFFh)

Unit

min.

max.

min.

max.

t300

CC SSC clock cycle time(2))

150

8TCL

262144 TCL

t301

CC SSC clock high time

–

t300 / 2 – 12

–

t302

CC SSC clock low time

–

t300 / 2 – 12

–

t303

CC SSC clock rise time

–

t304

CC SSC clock fall time

–

t305

CC Write data valid after shift edge

–

t306

CC Write data hold after shift edge(3)

– 2

–

– 2

–

t307p

Read data setup time before latch

edge, phase error detection on

(SSCPEN = 1)

37.5

–

2TCL + 12.5

–

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