LAN9252VSLASHML datasheet(180/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 180

 2015 Microchip Technology Inc.

11.2.16.26 PHY x Wakeup Filter Configuration Register A (PHY_WUF_CFGA_x)

Note 18:

ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the

PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set.

Index (In Decimal): 3.32785

Size:

16 bits

Bits

Description

Type

Default

Filter Enable

0 = Filter disabled

1 = Filter enabled

R/W/

NASR

Note 18

Filter Triggered

0 = Filter not triggered

1 = Filter triggered

R/WC/

NASR

Note 18

13:11

RESERVED

Address Match Enable

When set, the destination address must match the programmed address.

When cleared, any unicast packet is accepted. Refer to Section 11.2.9.4,

"Wakeup Frame Detection," on page 133 for additional information.

R/W/

NASR

Note 18

Filter Any Multicast Enable

When set, any multicast packet other than a broadcast will cause an address

match. Refer to Section 11.2.9.4, "Wakeup Frame Detection," on page 133

for additional information.

Note:

This bit has priority over bit 10 of this register.

R/W/

NASR

Note 18

Filter Broadcast Enable

When set, any broadcast frame will cause an address match. Refer to Sec-

tion 11.2.9.4, "Wakeup Frame Detection," on page 133 for additional informa-

tion.

Note:

This bit has priority over bit 10 of this register.

R/W/

NASR

Note 18

7:0

Filter Pattern Offset

Specifies the offset of the first byte in the frame on which CRC checking

begins for Wakeup Frame recognition. Offset 0 is the first byte of the incom-

ing frame’s destination address.

R/W/

NASR

Note 18

00h

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