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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32F412RGU6PTR 데이터시트(PDF) 113 Page - STMicroelectronics |
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STM32F412RGU6PTR 데이터시트(HTML) 113 Page - STMicroelectronics |
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113 / 201 page  DocID028087 Rev 7 113/201 STM32F412xE/G Electrical characteristics 166 6.3.10 PLL characteristics The parameters given in Table 45 and Table 46 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 16. Table 45. Main PLL characteristics Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock(1) -0.95(2) 12.10 MHz fPLL_OUT PLL multiplier output clock - 24 - 100 MHz fPLL48_OUT 48 MHz PLL multiplier output clock -- 48 75 MHz fVCO_OUT PLL VCO output - 100 - 432 MHz tLOCK PLL lock time VCO freq = 100 MHz 75 - 200 µs VCO freq = 432 MHz 100 - 300 Jitter(3) Cycle-to-cycle jitter System clock 100 MHz RMS - 25 - ps peak to peak - ±150 - Period Jitter RMS - 15 - peak to peak - ±200 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples. - 330 - IDD(PLL)(4) PLL power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design, not tested in production. 3. The use of two PLLs in parallel could degraded the Jitter up to +30%. 4. Guaranteed by characterization, not tested in production. |
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