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STM32F412RGU6PTR 데이터시트(PDF) 169 Page - STMicroelectronics |
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STM32F412RGU6PTR 데이터시트(HTML) 169 Page - STMicroelectronics |
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169 / 201 page ![]() DocID028087 Rev 7 169/201 STM32F412xE/G Package information 196 Device marking for WLCSP64 The following figure gives an example of topside marking and pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 62. WLCSP64 marking example (package top view) 1. Parts marked as “ES” or “E” or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. Table 100. WLCSP64 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 mm Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm |
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