STM32F412RGY3TR datasheet(157/201 Pages) STMICROELECTRONICS

157 / 201 page

DocID028087 Rev 7

157/201

STM32F412xE/G

Electrical characteristics

166

Synchronous waveforms and timings

Figure 54 through Figure 57 represent synchronous waveforms and Table 92 through

Table 95 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

•

BurstAccessMode = FSMC_BurstAccessMode_Enable;

•

MemoryType = FSMC_MemoryType_CRAM;

•

WriteBurst = FSMC_WriteBurst_Enable;

•

CLKDivision = 1; (0 is not supported, see the STM32F446 reference manual: RM0390)

•

DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

Table 90. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)

1. CL = 30 pF.

2. Based on characterization, not tested in production.

Symbol

Parameter

Min

Max

Unit

tw(NE)

FSMC_NE low time

4THCLK - 1

4THCLK+0.5

tv(NWE_NE)

FSMC_NEx low to FSMC_NWE low

THCLK

THCLK + 1

tw(NWE)

FSMC_NWE low time

2THCLK - 1 2THCLK + 0.5

th(NE_NWE)

FSMC_NWE high to FSMC_NE high hold time

THCLK - 1.5

tv(A_NE)

FSMC_NEx low to FSMC_A valid

tv(NADV_NE)

FSMC_NEx low to FSMC_NADV low

tw(NADV)

FSMC_NADV low time

THCLK – 0.5 THCLK+ 0.5

th(AD_NADV)

FSMC_AD(adress) valid hold time after

FSMC_NADV high)

THCLK

th(A_NWE)

Address hold time after FSMC_NWE high

THCLK- 1.5

th(BL_NWE)

FSMC_BL hold time after FSMC_NWE high

THCLK

tv(BL_NE)

FSMC_NEx low to FSMC_BL valid

1.5

tv(Data_NADV)

FSMC_NADV high to Data valid

THCLK + 2

th(Data_NWE)

Data hold time after FSMC_NWE high

THCLK + 0.5

Table 91. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)

1. CL = 30 pF.

2. Based on characterization, not tested in production.

Symbol

Parameter

Min

Max

Unit

tw(NE)

FSMC_NE low time

9THCLK - 1

9THCLK + 0.5

tw(NWE)

FSMC_NWE low time

7THCLK - 1

7THCLK + 0.5

tsu(NWAIT_NE)

FSMC_NWAIT valid before FSMC_NEx high

6THCLK -1

th(NE_NWAIT)

FSMC_NEx hold time after FSMC_NWAIT

invalid

4THCLK + 1

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