L9945 datasheet(111/144 Pages) STMICROELECTRONICS

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6.1.3

BIST & HWSC

The device features a Built-In Self-Test (BIST) and a HardWare Self-Check (HWSC).

For functional safety considerations, internal disable structures must operate always correctly and reliably. To

accomplish this, the disable sources paths and the VDD5 overvoltage detection block are self-checked by the

device:

•

BIST covers the digital domain of disable-related functions;

•

HWSC covers the analog domain of the VDD5 overvoltage comparator.

In case of BIST or HWSC failure, all channels except 7 and 8 are disabled. BIST is always followed by HWSC to

ensure full coverage of digital and analog domains. The sequence is performed in less than 3 ms, and is run:

•

After each NRES release (POR assertion does not imply BIST & HWSC sequence execution);

•

On demand, programming the BIST_RQ bit via SPI.

Note:

Due to device configuration reset during BIST, the procedure must be executed prior to channel configuration

applied.

The procedure starts with BIST. During BIST execution:

•

The BIST_DONE latch is set low;

•

All output drivers (including 7 and 8) are three-stated;

•

All the device registers are reset, except SPI latches (UV/OV events, disable events, etc.).

BIST checks the correct function of the disable logic to the gate drive of the outputs:

•

Switch OFF paths from DIS, NDIS, EN6, including the bidirectional NDIS output;

•

Switch OFF path from Communication Check;

•

Switch OFF path from HWSC/BIST;

•

Switch OFF path from OV/UV detection block.

BIST also checks that the implemented timers can be stopped (e.g. communication check timeout).

The BIST_DONE latch is set high once BIST has terminated.

•

In case the procedure detects an error, the BIST_DIS latch is set and all outputs, except 7 and 8, are kept

actively turned off. Channels 7 and 8 are kept in three-state.

•

In case BIST detected no error, the outputs are kept in three-state

HWSC follows BIST and checks the functionality of VDD5 overvoltage detection mechanism. HWSC lasts

tHWSC_DUR. During such interval, the outputs 1-6 are kept OFF actively by asserting the HWSC_DIS internal

signal; channels 7-8 are still in three-state, since the BIST executed previously. After tHWSC_DUR has expired, the

HWSC_DONE latch is set high and the self check result will be available via SPI reading the HWSC_DIS signal

status. Two cases can occur:

•

HWSC failed: the signal HWSC_DIS is kept high and disables (actively) all the outputs except 7 and 8;

•

HWSC passed: the signal HWSC_DIS is set low and the disable is released.

If both BIST and HWSC are successful, BIST_DIS and HWSC_DIS disable signals are released and the outputs

can be configured and enabled normally. If one among BIST and HWSC failed, channels 1-6 are kept disabled,

regardless of the configuration applied; channels 7-8 can still be enabled.

BIST and HWSC sequence is stopped in case of a reset condition:

•

NRES set low;

•

POR.

Note:

When configured as H-Bridge, channels 7 and 8 are handled like other channels and are disabled in case of

BIST/HWSC failure.

L9945

Safety & diagnostics

DS12275 - Rev 10

page 111/144

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