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IS25LE128E-RGLA3:P-TY 데이터시트(PDF) 139 Page - Integrated Silicon Solution, Inc

부품명 IS25LE128E-RGLA3:P-TY
상세설명  SERIAL FLASH MEMORY 133/166MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
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제조업체  ISSI [Integrated Silicon Solution, Inc]
홈페이지  http://www.issi.com
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IS25LE128E-RGLA3:P-TY 데이터시트(HTML) 139 Page - Integrated Silicon Solution, Inc

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IS25LE256E/128E
IS25WE256E/128E
Integrated Silicon Solution, Inc.- www.issi.com
139
Rev.A9
03/07/2023
Figure 8.92 FRQDTR AX Read Sequence (EDh [EXTADD=0], 3-byte address)
CE #
SCK
3-byte Address
0
1
2
3
4
5
6
7
8
9
10
11
Mode 3
Mode 0
tV
20 16 12
5 1
21 17 13
4 0
IO0
IO1
22 18 14
23 19 15
8 4
0
9 5
1
10 6
2
11 7
3
6 Dummy Cycles
IO2
IO3
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
5 1
4 0
6 2
7 3
Data
Out
Data
Out
Data
Out
Data
Out
5 1
4 0
6 2
7 3
Mode Bits
12
...
...
...
...
...
Notes:
1.
If the mode bits=AXh (where X is don’t care), it will keep executing the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.



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