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STM32F427AI 데이터시트(PDF) 182 Page - STMicroelectronics

부품명 STM32F427AI
상세설명  32b Arm® Cortex®-M4 MCUFPU, 225DMIPS, up to 2MB Flash/2564KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 com. interfaces, camera & LCD-TFT
PDF  240 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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STM32F427AI 데이터시트(HTML) 182 Page - STMicroelectronics

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Electrical characteristics
STM32F427xx STM32F429xx
182/240
DS9405 Rev 12
PC Card/CompactFlash controller waveforms and timings
Figure 63 through Figure 68 represent synchronous waveforms, and Table 99 and
Table 100 provide the corresponding timings. The results shown in this table are obtained
with the following FMC configuration:
•
COM.FMC_SetupTime = 0x04;
•
COM.FMC_WaitSetupTime = 0x07;
•
COM.FMC_HoldSetupTime = 0x04;
•
COM.FMC_HiZSetupTime = 0x00;
•
ATT.FMC_SetupTime = 0x04;
•
ATT.FMC_WaitSetupTime = 0x07;
•
ATT.FMC_HoldSetupTime = 0x04;
•
ATT.FMC_HiZSetupTime = 0x00;
•
IO.FMC_SetupTime = 0x04;
•
IO.FMC_WaitSetupTime = 0x07;
•
IO.FMC_HoldSetupTime = 0x04;
•
IO.FMC_HiZSetupTime = 0x00;
•
TCLRSetupTime = 0;
•
TARSetupTime = 0.
In all timing tables, the THCLK is the HCLK clock period.
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25)
0
-
ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low
-
0
ns
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high
THCLK−0.5
-
ns
td(CLKL-Data)
FMC_D[15:0] valid data after FMC_CLK low
-
2.5
ns
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low
0
-
ns
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high
THCLK−0.5
-
ns
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
4
-
-
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
0
-
-
1. CL = 30 pF.
2. Evaluated by characterization.
Table 98. Synchronous non-multiplexed PSRAM write timings(1)(2) (continued)
Symbol
Parameter
Min
Max
Unit



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