ST72361 datasheet(193/224 Pages) STMICROELECTRONICS

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ST72361

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12.9 I/O PORT PIN CHARACTERISTICS

12.9.1 General Characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

3. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to

IINJ(PIN) specification. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. Refer

to Section 12.2 on page 179 for more details.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. Configuration not recommended, all unused pins must be kept at a fixed voltage: Using the output mode of the I/O, for

example, or an external pull-up or pull-down resistor (see Figure 103). Data based on design simulation and/or technol-

ogy characteristics, not tested in production.

6. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-

scribed in Figure 104).

7. To generate an external interrupt, a minimum pulse width must be applied on an I/O port pin configured as an external

interrupt source.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage1)

CMOS ports

0.3 x VDD

VIH

Input high level voltage1)

0.7 x VDD

Vhys

Schmitt trigger voltage hysteresis2)

VIL

Input low level voltage1)

TTL ports

0.8

VIH

Input high level voltage1)

Vhys

Schmitt trigger voltage hysteresis2)

400

IINJ(PIN)

Injected Current on PB3

VDD = 5V

Flash devices

ROM devices

±4

Injected Current on any other I/O pin

±4

ΣIINJ(PIN)3)

Total injected current (sum of all I/O

and control pins)7)

±25

Ilkg

Input leakage current on robust pins See “10-BIT ADC CHARACTERISTICS” on page 204

Input leakage current4)

VSS ≤ VIN ≤ VDD

±1

µA

Static current consumption5)

Floating input mode

200

RPU

Weak pull-up equivalent resistor6)

VIN = VSS VDD = 5V

250

Ω

CIO

I/O pin capacitance

tf(IO)out

Output high to low level fall time

CL = 50pF

Between 10% and 90%

tr(IO)out

Output low to high level rise time

tw(IT)in

External interrupt pulse time7)

tCPU

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