R7KA8M2AFDCAC datasheet(155/295 Pages) RENESAS

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2.3.9

SCI Timing

Table 2.59

SCI timing (Asynchronous mode)

Conditions:

High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

If SCI pins are specified across the VCC I/O and VCC2 I/O, characteristics below is guaranteed only when VCC = VCC2.

Parameter

VCC/VCC2

Symbol

Min

Max

Unit

Note

Input clock cycle

1.62 V or above

tScyc

4.0

—

tTcyc

Figure 2.68

Input clock pulse width

1.62 V or above

tSCKW

0.4

0.6

tScyc

Input clock rise time

1.62 V or above

tSCKr

—

0.1*1

tScyc

Input clock fall time

1.62 V or above

tSCKf

—

0.1*1

tScyc

Output clock cycle

1.62 V or above

tScyc

6.0

—

tTcyc

Output clock pulse width

1.62 V or above

tSCKW

0.4

0.6

tScyc

Output clock rise time

2.70 V or above

tSCKr

—

3.3

1.62 V or above

—

6.6

Output clock fall time

2.70 V or above

tSCKf

—

3.3

1.62 V or above

—

6.6

Note:

tTcyc: TCLK cycle.

Note 1. 1 µs at the longest

tSCKW

tSCKr

tSCKf

tScyc

SCKn

Note:

n = 0 to 4, 9

Figure 2.68

SCK clock input/output timing

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 155 of 295

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