NRF52810-QFAA-R datasheet(385/483 Pages) NORDIC

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Peripherals

The RXD.AMOUNT and TXD.AMOUNT registers are updated when a granted transaction is completed.

The TXD.AMOUNT register indicates how many bytes were read from the TX buffer in the last transaction,

that is, ORC (over-read) characters are not included in this number. Similarly, the RXD.AMOUNT register

indicates how many bytes were written into the RX buffer in the last transaction.

The ENDRX event is generated when the RX buffer has been filled.

DEF

CPU

Free

CPUPENDING

CPU

Ignored

Granted

Ignored

DEF

CPU

Free

DEF

SPI master can use the DEF

character to stop the transaction as

soon as possible if the transaction is

not granted.

DEF

SPIS

Figure 102: SPI transaction when shortcut between END and ACQUIRE is enabled

6.19.4 Pin configuration

The CSN, SCK, MOSI, and MISO signals associated with the SPI slave are mapped to physical pins according

to the configuration specified in the PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers respectively.

If the CONNECT field of any of these registers is set to Disconnected, the associated SPI slave signal will not

be connected to any physical pins.

The PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers and their configurations are only used as

long as the SPI slave is enabled, and retained only as long as the device is in System ON mode, see POWER

— Power supply on page 61 chapter for more information about power modes. When the peripheral is

disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field

and PIN_CNF[n] register. PSEL.CSN, PSEL.SCK, PSEL.MOSI, and PSEL.MISO must only be configured when

the SPI slave is disabled.

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