NRF52810-QFAA-R datasheet(474/483 Pages) NORDIC

474 / 483 page

Hardware and layout

The DC supply voltage should be decoupled as close as possible to the VDD pins with high performance RF

capacitors. See the schematics for recommended decoupling capacitor values. The supply voltage for the

chip should be filtered and routed separately from the supply voltages of any digital circuitry.

Long power supply lines on the PCB should be avoided. All device grounds, VDD connections, and VDD

bypass capacitors must be connected as close as possible to the IC. For a PCB with a topside RF ground

plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground

plane, the best technique is to have via holes as close as possible to the VSS pads. A minimum of one via

hole should be used for each VSS pin.

Fast switching digital signals should not be routed close to the crystal or the power supply lines. Capacitive

loading of fast switching digital output lines should be minimized in order to avoid radio interference.

7.3.6 PCB layout example

The PCB layout shown as the example is a reference layout for the QFN48 package with internal LDO

setup.

Important: Pay attention to how the capacitor C3 is grounded. It is not directly connected to the

ground plane, but grounded via VSS pin 31. This is done to create additional filtering of harmonic

components.

For all available reference layouts, see Reference layout nRF52 Series.

Figure 133: Top silk layer

4430_161 v1.0

474

NRF52810-QFAA-R 데이터시트(PDF) 474 Page - Nordic Semiconductor