NRF52810-QFAA-R datasheet(211/483 Pages) NORDIC

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Peripherals

Peripheral 1

Peripheral 2

Peripheral 1

Peripheral 2

Event 1

Event 2

Event 1

Event 2

Event 3

Task 1

Task 2

Task 3

Task 1

CH[0].EEP

CH[1].EEP

CH[n].EEP

CH[0].TEP

CHEN

16MHz

FORK[0].TEP

CHG[0]

CHG[m]

...

Figure 46: PPI block diagram

The PPI system has, in addition to the fully programmable peripheral interconnections, a set of channels

where the event end point (EEP) and task end points (TEP) are fixed in hardware. These fixed channels can

be individually enabled, disabled, or added to PPI channel groups (see CHG[n] registers), in the same way

as ordinary PPI channels.

Instance

Channel

Number of channels

PPI

0-19

PPI (fixed)

20-31

Table 46: Configurable and fixed PPI channels

The PPI provides a mechanism to automatically trigger a task in one peripheral as a result of an event

occurring in another peripheral. A task is connected to an event through a PPI channel. The PPI channel

is composed of three end point registers, one EEP and two TEPs. A peripheral task is connected to a TEP

using the address of the task register associated with the task. Similarly, a peripheral event is connected to

an EEP using the address of the event register associated with the event.

On each PPI channel, the signals are synchronized to the 16 MHz clock, to avoid any internal violation

of setup and hold timings. As a consequence, events that are synchronous to the 16 MHz clock will be

delayed by one clock period, while other asynchronous events will be delayed by up to one 16 MHz clock

period.

Note that shortcuts (as defined in the SHORTS register in each peripheral) are not affected by this 16 MHz

synchronization, and are therefore not delayed.

4430_161 v1.0

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