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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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NRF52810-QFAA-R 데이터시트(PDF) 328 Page - Nordic Semiconductor |
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NRF52810-QFAA-R 데이터시트(HTML) 328 Page - Nordic Semiconductor |
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328 / 483 page  Peripherals 0x000 SysClk LFClk PRESC COUNTER X+1 First tick START >= ~15 us X+2 X+3 X 0 or more SysClk before Figure 87: Timing diagram - JITTER_START- 0x000 SysClk LFClk PRESC COUNTER First tick START <= ~250 us X+1 X+2 X Figure 88: Timing diagram - JITTER_START+ 6.16.9 Reading the COUNTER register To read the COUNTER register, the internal <<COUNTER>> value is sampled. To ensure that the <<COUNTER>> is safely sampled (considering an LFCLK transition may occur during a read), the CPU and core memory bus are halted for three cycles by lowering the core PREADY signal. The Read takes the CPU 2 cycles in addition resulting in the COUNTER register read taking a fixed five PCLK16M clock cycles. SysClk LFClk <<COUNTER>> N-1 N PREADY COUNTER_READ COUNTER X N 375.2 ns Figure 89: Timing diagram - COUNTER_READ 4430_161 v1.0 328 |
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