ST72F262G2B6 datasheet(167/171 Pages) STMICROELECTRONICS

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ERRATA SHEET

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– PB1=0, PC2=1, PB3=0 while CSS and PLL options are both disabled and PC4 is toggling

– PB1=0, PC2=1, PB3=0, PC4=1 while CSS or PLL options are enabled

This is detailed in the following table:

As a consequence, for cycle-accurate operations, these configurations are prohibited in either

input or output mode.

Workaround:

To avoid this occurring, it is recommended to connect one of these pins to GND (PC2 or PC4)

or VDD (PB1 or PB3).

19.3 16-BIT TIMER PWM MODE

In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC12R reg-

ister.

19.4 SPI MULTIMASTER MODE

Multi master mode is not supported.

19.5 MINIMUM OPERATING VOLTAGE

The minimum VDD voltage is 2.7V.

19.6 CSS FUNCTION

The Clock Security System is not guaranteed. The features described in Section 6.4.3 are

subject to revision.

19.7 INTERNAL AND EXTERNAL RC OSCILLATOR WITH LVD

If the LVD is disabled, the internal or external RC oscillator clock source cannot be used.

In ICP mode, new flash devices must be programmed with an external clock connected to the

OSC1 pin or using a crystal or ceramic resonator. In the STVP7 programming tool software,

select the “OPTIONS DISABLED” mode.

19.8 EXTERNAL CLOCK WITH PLL

The PLL option is not supported for use with external clock source.

CSS

PLL

PB1

PC2

PB3

PC4

Clock Disturbance

Toggling

Max. 2 clock cycles lost at each rising or

falling edge of PC4

xON

Max. 1 clock cycle lost out of every 16

ST72F262G2B6 데이터시트(PDF) 167 Page - STMicroelectronics