ST7FLITE25F2M6 datasheet(107/131 Pages) STMICROELECTRONICS

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EMC CHARACTERISTICS (Cont’d)

13.7.4 ESD Pin Protection Strategy

To protect an integrated circuit against Electro-

Static Discharge the stress must be controlled to

prevent degradation or destruction of the circuit el-

ements. The stress generally affects the circuit el-

ements which are connected to the pads but can

also affect the internal devices when the supply

pads receive the stress. The elements to be pro-

tected must not receive excessive current, voltage

or heating within their structure.

An ESD network combines the different input and

output ESD protections. This network works, by al-

lowing safe discharge paths for the pins subjected

to ESD stress. Two critical ESD stress cases are

presented in Figure 69 and Figure 70 for standard

pins.

Standard Pin Protection

To protect the output structure the following ele-

ments are added:

– A diode to VDD (3a) and a diode from VSS (3b)

– A protection device between VDD and VSS (4)

To protect the input structure the following ele-

ments are added:

– A resistor in series with the pad (1)

– A diode to VDD (2a) and a diode from VSS (2b)

– A protection device between VDD and VSS (4)

Figure 69. Positive Stress on a Standard Pad vs. VSS

Figure 70. Negative Stress on a Standard Pad vs. VDD

VDD

VSS

(1)

(2a)

(2b)

(4)

OUT

VDD

VSS

(3a)

(3b)

Main path

Path to avoid

VDD

VSS

(1)

(2a)

(2b)

(4)

OUT

VDD

VSS

(3a)

(3b)

Main path

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