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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST92163 데이터시트(PDF) 205 Page - STMicroelectronics |
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ST92163 데이터시트(HTML) 205 Page - STMicroelectronics |
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205 / 224 page  205/224 ST92163 - ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS (Cont’d) 1)The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the unde- fined region of the falling edge of SCL 2)The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal Cb = total capacitance of one bus line in pF I 2C Bus Timings Parameter Symbol Standard I 2C Fast I 2C Unit Min Max Min Max Bus free time between a STOP and START con- dition TBUF 4.7 1.3 ms Hold time START condition. After this period, the first clock pulse is generated THD:STA 4.0 0.6 µs LOW period of the SCL clock TLOW 4.7 1.3 µs HIGH period of the SCL clock THIGH 4.0 0.6 µs Set-up time for a repeated START condition TSU:STA 4.7 0.6 µs Data hold time THD:DAT 0 (1) 0 (1) 0.9(2) ns Data set-up time TSU:DAT 250 100 ns Rise time of both SDA and SCL signals TR 1000 20+0.1Cb 300 ns Fall time of both SDA and SCL signals TF 300 20+0.1Cb 300 ns Set-up time for STOP condition TSU:STO 4.0 0.6 ns Capacitive load for each bus line Cb 400 400 pF |
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