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ST92F120JR1T 데이터시트(PDF) 255 Page - STMicroelectronics

부품명 ST92F120JR1T
상세설명  8/16-BIT FLASH MCU FAMILY WITH RAM, EEPROM AND J1850 BLPD
PDF  320 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST92F120JR1T 데이터시트(HTML) 255 Page - STMicroelectronics

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J1850 Byte Level Protocol Decoder (JBLPD)
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Figure 117. Local Loopback structure
10.8.3.8 Peripheral clock management
To work correctly, the encoder and decoder sec-
tions of the peripheral need an internal clock at
1MHz. This clock is used to evaluate the protocol
symbols timings in transmission and in reception.
The prescaled clock is obtained by dividing the
MCU internal clock frequency. The CLKSEL regis-
ter allows the selection of the right prescaling fac-
tor. The six least significant bits of the register
(FREQ[5:0]) must be programmed with a value us-
ing the following formula:
MCU Internal Freq. = 1MHz * (FREQ[5:0] + 1).
Note: If the MCU internal clock frequency is lower
than 1MHz, the JBLPD is not able to work correct-
ly. If a frequency lower than 1MHz is used, the
user program must disable the JBLPD.
Note: When the MCU internal clock frequency or
the clock prescaler factor are changed, the JBLPD
could lose synchronization with the J1850 bus.
Passive state
VPWO from the
peripheral logic
VPWI toward the
J1850 decoder
Polarity
manager
OPTI ONS.INPOL
OPTIO NS.LOOPB
MCU VPWO
pin
MCU VPWI
pin
JBLPD peripheral
MCU
9



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