ADE75 datasheet(132/148 Pages) AD

132 / 148 page

ADE75xx/ADE71xx

Preliminary Technical Data

Rev. PrE | Page 132 of 148

The MSB of the SPI outputs is transmitted first

The LSB of the SPI outputs is transmitted first

Reserved

This bit must be kept as 1.

Table 132. SPI Interrupt Status Register SFR (SPISTAT, 0xEA)

Bit

Location

Interrupt Flag

Default

Value

Description

SPI Peripheral Busy Flag

The SPI peripheral is idle

BUSY

The SPI peripheral is busy transferring data in slave or master mode.

SPI Multi-Master Error Flag

A multiple master error has not occurred.

MMERR

If the SS_EN bit is set, enabling the Slave Select input and the SS is asserted

while the SPI peripheral is transferring data as a master, then this flag is raised

to indicate the error. Write a zero to this bit to clear it..

SPI Receive Overflow Error Flag.

Reading the SPI2CRx SFR will clear this bit.

SPIRxOF

The SPI2CRX register contains valid data

SPIRxOF

This bit is set if the SPI2CRX register is not read before the end of the

next byte transfer. If the RxOF_EN bit is set and this condition occurs,

SPI2CRX will be overwritten.

Reserved

SPIRxBF

Status bit for SPI Rx buffer. When set the Rx FIFO is full. Reading the SPI2CRx SFR will

clear this bit.

SPITxUF

Status bit for SPI Tx buffer. When set the Tx FIFO is underflowing and data can be write

into SPI2CTx. Write a zero to this bit to clear it.

SPI Transmit Interrupt Flag.

SPITxIRQ

The SPI2CTX register is full.

SPITxIRQ

This bit is set when the SPI2CTX register is empty. If the SPI/I2C

interrupt is enabled, an interrupt will be generated when this bit is set.

If new data isn’t written into the SPI2CTX SFR before the end of the

current byte transfer, the transfer will stop and the SS will be

deasserted. Write a zero to this bit to clear it..

SPITxBF

Status bit for SPI Tx buffer. When set, the SPI Tx buffer is full. Write a zero to this bit to

clear it..

SPI PINS

MISO (Master In, Slave Out Data I/O Pin)

The MISO pin is configured as an input line in master mode

and as an output line in slave mode. The MISO line on the

master (data in) should be connected to the MISO line in the

slave device (data out).The data is transferred as byte-wide (8-

bit) serial data, MSB first.

MOSI (Master Out, Slave In Pin)

The MOSI pin is configured as an output line in master mode

and as an input line in slave mode. The MOSI line on the master

(data out) should be connected to the MOSI line in the slave

device (data in).The data is transferred as byte-wide (8-bit)

serial data, MSB first.

SCLK (Serial Clock I/O Pin)

The master serial clock (SCLK) is used to synchronize the data

being transmitted and received through the MOSI and MISO

data lines. The SCLK pin is configured as an output in master

mode and as an input in slave mode.

In master mode, the bit rate, polarity, and phase of the clock are

controlled by the SPI Configuration Register SFR (SPIMOD1,

0xE8)

and SPI Configuration Register SFR (SPIMOD2, 0xE9).

In slave mode, the SPI Configuration Register SFR (SPIMOD2,

0xE9)

must be configured with the phase and polarity of the

expected input clock.

In both master and slave modes, the data is transmitted on one

edge of the SCLK signal and sampled on the other. It is

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