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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST72334J2TA/XXX 데이터시트(PDF) 139 Page - STMicroelectronics |
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ST72334J2TA/XXX 데이터시트(HTML) 139 Page - STMicroelectronics |
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139 / 150 page  ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 139/150 15.12 8-BIT ADC CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Figure 97. Typical Application with ADC Notes: 1. Unless otherwise specified, typical data is based on TA=25°C and VDD-VSS=5V. They are given only as design guide- lines and are not tested. 2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS. 3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k Ω). Data based on characterization results, not tested in production. 4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then always valid. Symbol Parameter Conditions Min Typ 1) Max Unit fADC ADC clock frequency 4 MHz VAIN Conversion range voltage 2) VSSA VDDA V RAIN External input resistor 10 3) k Ω CADC Internal sample and hold capacitor 6 pF tSTAB Stabilization time after ADC enable fCPU=8MHz, fADC=4MHz 0 4) µs tADC Conversion time (Sample+Hold) 3 - Sample capacitor loading time - Hold conversion time 4 8 1/fADC AINx ST72XXX CIO ~2pF VDD IL ±1µA VT 0.6V VT 0.6V VAIN RAIN VDDA VSSA 0.1µF VDD ADC |
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