 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
M38041F8HKP 데이터시트(PDF) 112 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
M38041F8HKP 데이터시트(HTML) 112 Page - Renesas Technology Corp |
|
|
112 / 116 page  Rev.1.01 Jan 25, 2005 page 112 of 114 REJ03B0131-0101Z 3804 Group (Spec. H) Table 32 Multi-master I2C-BUS bus line characteristics Fig. 96 Timing diagram of multi-master I2C-BUS tBUF tHD:STA tHD:DAT tLOW tR tF tHIGH tsu:DAT tsu:STA tHD:STA tsu:STO SCL P S Sr P SDA S: START condition Sr: RESTART condition P: STOP condition Symbol Parameter Unit Bus free time Hold time for START condition Hold time for SCL clock = “0” Rising time of both SCL and SDA signals Data hold time Hold time for SCL clock = “1” Falling time of both SCL and SDA signals Data setup time Setup time for repeated START condition Setup time for STOP condition tBUF tHD;STA tLOW tR tHD;DAT tHIGH tF tSU;DAT tSU;STA tSU;STO Min. Max. Min. Max. µs µs µs ns µs µs ns ns µs µs Standard clock mode High-speed clock mode Note: Cb = total capacitance of 1 bus line 4.7 4.0 4.7 0 4.0 250 4.7 4.0 1000 300 1.3 0.6 1.3 20+0.1Cb 0 0.6 20+0.1Cb 100 0.6 0.6 300 0.9 300 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
