M32CSLASH86T datasheet(123/505 Pages) RENESAS

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11. Interrupts

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11.4 High-Speed Interrupt

The high-speed interrupt executes an interrupt sequence in five cycles and returns from the interrupt in

three cycles.

When the FSIT bit in the RLVL register is set to "1" (interrupt priority level 7 available for the high-speed

interrupt), the ILVL2 to ILVL0 bits in the interrupt control registers can be set to "1112" (level 7) to use the

high-speed interrupt.

Only one interrupt can be set as the high-speed interrupt. When using the high-speed interrupt, do not set

multiple interrupts to interrupt priority level 7. Set the DMAII bit in the RLVL register to "0" (interrupt priority

level 7 available for interrupts).

Set the starting address of the high-speed interrupt routine in the VCT register.

When the high-speed interrupt is acknowledged, the FLG register is saved into the SVF register and PC is

saved into the SVP register. The program is executed from an address indicated by the VCT register.

Execute the FREIT instruction to return from the high-speed interrupt routine.

The values saved into the SVF and SVP registers are restored to the FLG register and PC by executing the

FREIT instruction.

The high-speed interrupt and the DMA2 and DMA3 use the same register. When using the high-speed

interrupt, neither DMA2 nor DMA3 is available. DMA0 and DMA1 can be used.

11.5 Interrupts and Interrupt Vectors

There are four bytes in one vector. Set the starting address of interrupt routine in each vector table. When

an interrupt request is acknowledged, the interrupt routine is executed from the address set in the interrupt

vectors.

Figure 11.2 shows the interrupt vector.

Figure 11.2 Interrupt Vector

Middle-order bits of an address

Low-order bits of an address

High-order bits of an address

0 0 16

Vector Address + 0

Vector Address + 1

Vector Address + 2

Vector Address + 3

LSB

MSB

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