M16CSLASH62 datasheet(414/615 Pages) RENESAS

414 / 615 page

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-97

UART

Example of wiring

Figure 2.5.17. Operation timing of reception in UART mode (used for SIM interface)

Microcomputer

SIM card

TxD2

RxD2

Example of operation (when direct format)

Receive enable

bit(RE)

Receive

complete flag(RI)

D0 D1 D2 D3

D4 D5 D6

Start

bit

Parity

bit

TXD2 (Note)

“0”

“1”

“0”

“1”

Receive interrupt

request bit(IR)

“0”

“1”

Cleared to “0” when interrupt request is accepted, or cleared by software

D0 D1 D2 D3 D4 D5 D6 D7

Transfer clock

Since a parity error occurred, the

“L” level returns from TxD2

RXD2 (Note)

Read to receive buffer

D0 D1 D2 D3

D4 D5 D6

Signal line level

(Note)

D0 D1 D2 D3 D4 D5 D6 D7

Note: TxD2 and RxD2 are connected in the manner of wired OR as shown in the connection diagram. So TxD2 and RxD2 ought to

become the same signal from the logical standpoint, but the output signals turn complex, so they are shown separately. Also,

the signal level resulting from connecting TxD2 and RxD2 is shown as a signal line level.

(1) Reception enabled

(2) Start reception

(3) Receiving is completed

(4) Data is read

Stop

bit

(5) Parity error occurred

The above timing applies to the following settings :

• Parity is enabled.

• One stop bit.

• Transmit interrupt cause select bit = “1”.

Tc = 16 (n + 1) / fi

fi : frequency of BRG2 count source (f1, f8, f32)

n : value set to BRG2

Shown in ( ) are bit symbols.

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