M16CSLASH62 datasheet(149/615 Pages) RENESAS

149 / 615 page

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock asynchronous serial I/O (UART) mode

1-130

Figure 1.16.18. Typical transmit timings in UART mode(UART2)

Start

bit

Parity

bit

Cleared to “0” when interrupt request is accepted, or cleared by software

Stop

bit

Data is set in UART2 transmit buffer register

Transferred from UART2 transmit buffer register to UARTi transmit register

Transmit enable

bit(TE)

Transmit buffer

empty flag(TI)

Transmit register

empty flag (TXEPT)

“0”

“1”

“0”

“1”

“0”

“1”

Transmit interrupt

request bit (IR)

“0”

“1”

Transfer clock

TxD2

The above timing applies to the following settings :

• Parity is enabled.

• One stop bit.

• Transmit interrupt cause select bit = “1”.

Tc = 16 (n + 1) / fi

fi : frequency of BRG2 count source (f1, f8, f32)

n : value set to BRG2

Shown in ( ) are bit symbols.

Note

Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.

• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)

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