M16CSLASH62 datasheet(219/615 Pages) RENESAS

219 / 615 page

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 3V)

1-200

Memory Expansion Mode and Microprocessor Mode

(When accessing external memory area with wait, and select multiplexed bus)

Measuring conditions :

• VCC=3V

• Input timing voltage : Determined with VIL=0.48V,VIH=1.5V

• Output timing voltage : Determined with VOL=1.5V,VOH=1.5V

Read timing

Write timing

0ns.min

BCLK

CSi

ALE

60ns.max

–4ns.min

th(BCLK–CS)

4ns.min

tcyc

ADi

BHE

80ns.max

th(BCLK–DB)

4ns.min

td(DB–WR)

(tcyc*3/2–80)ns.min

ADi

/DBi

Address

Data output

(tcyc/2)ns.min

Address

(tcyc/2–60)ns.min

td(BCLK–ALE)

td(BCLK–WR)

4ns.min

BCLK

CSi

td(BCLK–CS)

60ns.max

ALE

4ns.min

th(BCLK–CS)

4ns.min

tcyc

ADi

BHE

ADi

/DBi

th(RD–DB)

0ns.min

Address

(tcyc/2)ns.min

Data input

Address

tac3(RD–DB)

tdz(RD–AD)

8ns.max

td(AD–RD)

0ns.min

td(AD–WR)

WR,WRL,

WRH

th(RD–CS)

td(AD–ALE) (tcyc/2–45)ns.min

tSU(DB–RD)

80ns.min

th(ALE–AD)

50ns.min

td(BCLK–AD)

60ns.max

td(BCLK–ALE)

th(BCLK–ALE)

–4ns.min

(tcyc/2)ns.min

th(RD–AD)

th(BCLK–AD)

th(BCLK–RD)

0ns.min

td(BCLK–RD)

60ns.max

td(BCLK–CS)

60ns.max

th(WR–CS)

(tcyc/2)ns.min

td(BCLK–DB)

td(AD–ALE)

td(BCLK–AD)

60ns.max

th(WR–DB)

(tcyc/2)ns.min

th(BCLK–AD)

th(WR–AD)

th(BCLK–WR)

th(BCLK–ALE)

0ns.min

60ns.max

VCC = 3V

Figure 1.23.12. VCC = 3V timing diagram (5)

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