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M16C/62 데이터시트(PDF) 305 Page - Renesas Technology Corp |
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M16C/62 데이터시트(HTML) 305 Page - Renesas Technology Corp |
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305 / 615 page ![]() Timing Mitsubishi microcomputers M16C / 62M Group (Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1-286 Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 3), CM15 = “1” unless otherwise specified) Table 1.31.21. Memory expansion and microprocessor modes (with no wait) td(BCLK-AD) Address output delay time 60 ns td(BCLK-CS) Chip select output delay time 60 ns th(BCLK-AD) Address output hold time (BCLK standard) 4 ns th(BCLK-CS) Chip select output hold time (BCLK standard) 4 ns td(BCLK-ALE) ALE signal output delay time 60 ns th(BCLK-ALE) ALE signal output hold time – 4 ns td(BCLK-RD) RD signal output delay time 60 ns th(BCLK-RD) RD signal output hold time 0 ns th(RD-AD) Address output hold time (RD standard) 0 ns td(BCLK-WR) WR signal output delay time 60 ns th(BCLK-WR) WR signal output hold time 0 ns th(WR-AD) Address output hold time (WR standard) 0 ns td(BCLK-DB) Data output delay time (BCLK standard) 80 ns th(BCLK-DB) Data output hold time (BCLK standard) 4 ns td(DB-WR) Data output delay time (WR standard) (Note1) ns th(WR-DB) Data output hold time (WR standard)(Note2) 0 ns Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = f(BCLK) X 2 10 9 – 80 [ns] Symbol Standard Measuring condition Max. Min. Parameter Unit Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1k Ω, hold time of output “L” level is t = – 30pF X 1k Ω X ln (1 – 0.2VCC / VCC) = 6.7ns. DBi R C Note 3: Specify a product of –40°C to 85°C to use it. P6 P7 P8 P10 P9 P0 P1 P2 P3 P4 P5 30pF Figure 1.31.1. Port P0 to P10 measurement circuit Figure 1.31.1 |
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